Sr. ASIC Design Engineer

Santa Clara, California

This job has expired.

Sr. ASIC Design Engineer If you are a Sr. ASIC Design Engineer with experience, please read on!

*Job Title:* Sr. ASIC Design Engineer
*Job Location:* San Jose, CA or Austin, TX - relocation assistance offered!
*Compensation:* $150K - $225K base Depending on experience

We are a well-funded Smart Interconnect technology company focused on enabling efficient and performant composable architectures to enable flexible, scalable, low latency composable systems. We provide silicon, hardware, and software which leverages the Compute Express Link (CXL) interconnect standard to provide high-performance connectivity to a broad ecosystem of components. We are a next-generation infrastructure company addressing a $500 billion dollar market composed of on-prem, edge data center, and core data center equipment.
Top Reasons to Work with Us 1) Competitive Compensation ($150K - $225K base Depending on Experience)
2) Comprehensive Benefits package including stock options and relocation assistance!
3) The chance to join a small start-up tackling challenging problems with huge upside potential!
What You Will Be Doing As a member of the SoC Design team, you will be responsible for the following:

- Microarchitecture of high-performance (low-latency, high-bandwidth, high-frequency), low-power on-chip modules design
- The design job includes microarchitecture, design and writing the RTL code, connectivity, performing structural checks (such as Lint, CDC) of the modules
- Develop and maintain methodology/flows/checks for designs
- Work with multi-disciplinary groups to deliver the modules, close the static timing and work with backend engineers to close the timing
What You Need for this Position Must have a BSEE / MSEE or similar degree with 5 - 15+ years experience with the following:

- Design and Verification of multi-million gate ASICs with Verilog or System Verilog
- Hands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies
- Experience with multiple clock domains and asynchronous interfaces
- Experience or knowledge of system architecture, CPU & IP integration, power and clock domains
- Familiarity with software and operating systems concepts
- Computer Architecture concepts
- SoC system bus/fabric/interconnect design verification
- Memory controller design verification
- Expertise in System Verilog and other high level languages like C, C++ is a must
- Should have knowledge of AMBA protocols - AXI, AHB, APB, and other Management interfaces
- Familiarity with scripting languages such as Perl, Python
So, if you are a Sr. ASIC Design Engineer with experience, please apply today! or send an updated copy of your resume to ** for immediate consideration!
- Applicants must be authorized to work in the U.S.

*CyberCoders, Inc is proud to be an Equal Opportunity Employer*

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, protected veteran status, or any other characteristic protected by law.

*Your Right to Work* - In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification document form upon hire.

This job has expired.

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