Physical Design Engineer-Staff Level-ASIC-Verilog/System Verilog
CyberCoders

Milpitas, California

This job has expired.


Physical Design Engineer-Staff Level-ASIC-Verilog/System Verilog If you are a Physical Design Engineer-Staff Level-ASIC-Verilog/System Verilog with experience, please read on!
What You Will Be Doing (THIS POSITION REPORTS TO MILPITAS 3 DAYS A WEEK AND IS PARTIAL REMOTE, SIGN ON BONUSES ARE AVAILABLE TO HELP MOVE TO THE AREA)
Primary Responsibilities:

" Overall design support to ASIC customers with emphasis on Front-end and Physical design
" Perform Physical synthesis, timing feasibility analysis and SDC validation at block-level and top-level
" Review block-level/top-level clock specifications for completeness and feasibility
" Handle all the Physical design tasks (Floorplanning, Placement, Clocktree synthesis, Routing and Timing closure)
" Perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis and Physical Verification)

Necessary Qualifications:

" BSEE/MSEE, with 10+ years of experience. MSEE preferred
" Strong experience in Synthesis, Physical Design and STA; Experience in an SoC product development organization with tape-out experience at 28nm/16nm/7nm design nodes
" Understanding the full scope of customers design and support all design integration tasks
" Hands-on experience with synthesis tools like Design Compiler/Genus and physical implementation tools like ICC2/Innovus
" Strong problem-solving skills and ability to analyze and resolve timing/physical design issues is required
" Experience with power analysis and IR-drop tools (primepower/Redhawk/Voltus) and Static Timing Analysis (Primetime/Tempus)
" Experience with Physical Verification and fix PV errors in layout
" Expert handling of Verilog HDL based Netlists, Physical design libraries, Scripting (Perl/Tcl/Python) is required
" Good understanding of ASIC front-end design and working knowledge of Verilog/System Verilog
" Team player with good interpersonal and communication skills
What You Need for this Position - Physical Design Engineer
- ASIC
- Verilog
- System Verilog
- Physical Design
- SDC validation
- Physical Verification
- ASIC Physical Design
- Electrical Engineer
So, if you are a Physical Design Engineer-Staff Level-ASIC-Verilog/System Verilog with experience, please apply today!
Colorado employees will receive paid sick leave. For additional information about available benefits, please contact Jonathan Gilmor
- Applicants must be authorized to work in the U.S.



*CyberCoders, Inc is proud to be an Equal Opportunity Employer*



All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, protected veteran status, or any other characteristic protected by law.



*Your Right to Work* - In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification document form upon hire.


This job has expired.

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